1. Field of the Invention
The present invention relates to an analytical simulator and to an analytical simulation method and program used for analyzing failure in an electronic circuit or the like, and in particular, relates to those suitably used for analyzing failure in a semiconductor device.
2. Description of the Related Art
Conventionally, a failure analysis method for detecting a defective portion in a semiconductor device is known, in which a specific signal is input into a logic circuit of the semiconductor device, and the output signal from the logic circuit is electrically measured. If this electrically-measured output signal (i.e., observed value) does not coincide with a logically-calculated output signal (i.e., expected output value) corresponding to the input signal, then it is determined that the logic circuit is defective.
Generally, the logic circuit of the semiconductor device is divided into blocks and a test pattern as an input signal for each block is prepared in advance. The expected output value and the observed value are compared with each other for each block, thereby roughly determining the portion which has a defect. In addition, the output signal is measured by (i) making a needle directly contact the wiring of the logic circuit, or (ii) using an electronic-beam tester for performing non-contact measurement.
However, in order to accurately determine the portion which has a defect in the logic circuit of the semiconductor device, the target portion at which the output signal is measured should be experimentally estimated, or the output signals should be measured at many portions. Therefore, skilled technique or a very long working time is necessary.
Accordingly, in order to accurately determine the portion which has a defect in the logic circuit of the semiconductor device, the logic circuit should be divided into many small circuits which correspond to different functions or the like, and a test pattern should be prepared as an input signal into each divided circuit. The output signal from each divided circuit should be measured so as to extract a target circuit which has a defect, and signals on wiring lines in the target circuit should be checked so as to detect the defective portion. Such determination of the defective portion is difficult and time-consuming, in particular, for semiconductor devices having complicated and large-scale logic circuits. That is, comparison between the expected output signal and the measured output signal must be repeated many times.